Universal Logic : Mux to Logic gates conversion
Posted by Nityanand Dubey on January 7, 2010
We have seen the universal gates in out previous posts. The NAND and NOR are called the universal gates because they can create any of the logic gates.
There is an another concept called “Universal Logic”, Universal logic can also be used to create any of the logic gates.
MUX and Decoders are called “Universal Logic”
In this post, we will see haw a 2:1 MUX can be used to create different logic gates.
1. Designing an Inverter using 2:1 MUX.
To design an inverter using 2:1 mux, we have to use the input as the select line of the MUX and the “zeroth” select line would be tied with “Logic 1 ” and “First” select line would be tired with “Logic 0″, Now when the select line (Input) goes to “1″ the out put will be “0″ ( inverted).
Image : MUX to inverter -
2. Designing an AND Gate using 2:1 MUX.
To design an AND using 2:1 mux, we need to tie the “zeroth” input to “Logic 0″ and the “First” input to the one of the input of the AND Gate. The other input of AND gate would be connected with the select line of the MUX.
Now, the out put of the MUX would be “1″ only if the both of the inputs are “1″ otherwise it would be “0″ for all conditions.
Image : MUX to AND Gate -
3. Designing an OR Gate using 2:1 MUX.
To design an OR using 2:1 mux, we need to tie the “First” input to “Logic 1″ and the “Zeroth” input to the one of the input of the OR Gate. The other input of OR gate would be connected with the select line of the MUX.
Now, the output of the MUX would be “1″ when any oth the two inputs would be “1″ otherwise it would be “0″ for all conditions.
Image : MUX to OR Gate -
4. Designing an NOR Gate using 2:1 MUX.
To design the NOR using 2:1 mux, we need to tie the “Zeroth” input of mux to one of the input of NOR and another input of MUX is tied to “0″ . The another input of NOR gate would be applied to the select line of the MUX.
Now, the output of the MUX would be A’B’ = (A+B)’. which is as same as the output of NOR Gate.
Image : MUX to NOR Gate -
5. Designing an NAND Gate using 2:1 MUX.
To design the NAND using 2:1 mux, we need to combine the AND Gate and inverter implementation
6. Designing an XOR Gate using 2:1 MUX.
To design the XOR using 2:1 mux, we need to tie the “Zeroth” input of mux to one of the input of XOR and another input of MUX to the inverted of first input. The another input of XOR gate would be applied to the select line of the MUX.
Now, the output of the MUX would be AB’ + A’B which is as same as the output of XOR Gate.
Image : MUX to XOR Gate -
7. Designing an XNOR Gate using 2:1 MUX.
To design the XNOR using 2:1 mux, we need to tie the “First” input of mux to one of the input of XOR and another input of MUX to the inverted of first input. The another input of XOR gate would be applied to the select line of the MUX.
Now, the output of the MUX would be A’B’ + AB which is as same as the output of XNOR Gate.
Image : MUX to XNOR Gate -







Sounderrajan said
In NOR implementation, the input of mux is A’. It was misprinted as A.
Sounderrajan..
veeru said
hi
Shantanu Saha said
its really a very effective and fruitful topic.
could you please discuss the design of higher order mux from lower order.
Gerald said
Thanks a lot for making the effort, NOR implementation has a gaffe please rectify that
piedpiper67 said
Very helpful post.
Would help even more if you posted the inner construction of the 2-1 MUXer (1 NOT gate, 2 AND gates, 1 OR gate)
That way one would see exactly why all the stuff you describe happens.
Subash John said
The NOR gate implementation is wrong…Instead inputs should be 1 & A’.
Subash John said
The above inputs were for NAND gate and not for NOR gate….For NOR we have A & 1 as inputs.
Namit said
This work helped, I would like to know more possible applications of 2:1 mux
pranesh madeti said
thanks a lot
Salman Javaid said
Can there be a 4 Input And Gate from a 4 into 1 Mux?
Ankit Jain said
I think something is wrong with MUX to NOR Gate.
Bapun said
Nice site.i like it.
PARTHIBAN.P.R said
thanks a lot for clearing my dout
but here one implementation is wrong in NOR gate we have to give A’ instead of A that is only the mistake pls rectify it
once agin thaks to your team to created this
Rohit Murarka said
Yes, that’s correct. Even I was stuck for a while and figured out same issue. Anyways the overall post is great and have helped me a lot to think differently!!!
cury said
design 1:2 demux using 2:1 mux?
Safdar said
Thanks for the info sir.I would be grateful to you if you provide the detailed explanation of any of the above examples.
ISHITA said
AWESOME!
tHANKS A TON!
“NOW I HAVE MUX IN MY POCKET”-GHANSHYAM PRABHU(LAB TEACHER ICT DEPT SEC-C!)
Dnyaneshwar said
DNYANESHWAR SAHANE
Brilliant note.
” After that I will never forget this things”
sushmita said
great work sir. thanxxx a lot. just rectify the nor gate plzzzzz!!!!!
papu said
THANKS
HASSAN said
would also be nice if the logic function has been declared so.
Thanks..
kothasreekanthreddy said
implement different fliop and counters
chandra shekhar yadav said
u r correct : for nor implimentation it is A’
Vky Vikas said
The NOR implementation has to be corrected by the admin ..
sumathi said
Good work.. It helped me a lot.. Thank u..
Bhavya said
its really helpful….thanks a lot
Mohit Sharma said
Am trying to design 3 input XOR gate using 2:1 mux. but could’t make it. If some one knows than pls help……….
Nityanand Dubey said
@Mohit,
You can use Two 2:1 Muxes to create 3 input XOR. As similar as using Two (2 input) XOR Gate to create 1 (Three Input) XOR