What is the difference between signals and variables

There are three major difference between a signal and a variable in the VHDL

 Coverage wise –

Signals has coverage to whole architecture, it can be access from any place in a Architecture of entity

A variable is local to a procedure defined in the architecture

Behavior wise –

Signal assignments executes concurrently, It means, if we have 5 signals assignment, then it depends on the simulator to decide which signal to be assigned first

In case of variable, it takes the value immediately OR in other language, it executes sequentially

Synthesis Wise –

If we have 2 variable and two signals used in a process, the variables infer just a wire during synthesis, but the signals infer a Flop.

 Also you can say that – the number of flops inferred by a process is roughly equal to the number of signals used in it (in Left had side)