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Archive for July, 2008

Design an Inverter and a Pass Gate ( Buffer) using the XOR gate

Posted by Nityanand Dubey on July 27, 2008

The X-OR gate can be used as a Pass Gate and as an inverter. As per characteristic of an Inverter, the output should have opposite value of the input
Lets look into the given figure

Digital : Image – XOR as Inverter

 

From the given Image –

One of the inputs of XOR gate is tied with Logic Value 1. Lets see whether it would works as an Inverter or not

From the output equation of the XOR Gate –

 

Y = AB’ + A’B

Where
A and B are two Inputs to the XOR Gate and Y is the Output

According to the diagram, One input is tied with Logic ‘1’

=> Y = A.(1)’+ A’.1
=> Y = 0 + A’
=> Y = A’

Summary : If we tie one input of an XOR Gate with Logic value ‘1’ then XOR works as an Inverter

The X-OR gate can also be used as a pass Gate or a buffer that means it can be used to transmit the same input signal to the output.

Let look into the given figure

Digital : Image – XOR as Pass Gate

 

From the given Image –

One of the inputs of XOR gate is tied with Logic Value 0.
From the output equation of the XOR Gate –

Y = AB’ + A’B

Where
A and B are two Inputs to the XOR Gate and Y is the Output

According to the diagram, One input is tied with Logic ‘0’

=> Y = A.(0)’+ A’.0
=> Y = A + 0
=> Y = A

 

 

Summary : If we tie one input of an XOR Gate with Logic value ‘0’ then XOR works as a buffer that mean whatever we give at the input, same would appear at the output

 

Posted in Digital Design | Tagged: , , , , , | 1 Comment »

What is sensitivity list in verilog?

Posted by Nityanand Dubey on July 20, 2008

 

 

  A simple always block runs forever it means as it touches the “end” again starts from beginning.Sensitivity list is a medium to make a controlled always block.
 
Example of normal always block
 
    always
    begin
        // statements
    end

 

     always @ ( sensitivity list)
      begin
           // statements
      end

 

The syntax of sensitivity list can be –
 
     A. always @ ( x or y or z)
     B. always @ ( posedge x )
     C. always @ ( posedge x or A )
     D. always @ ( posedge x or negedge y )
     E. always @ ( x, y, z)
     F. always @(*)
     G. always @*
    
The E, F and G are the new constructs added in the verilog 2001.

Usage of different syntaxes in verilog –

Point A and E are same in behavior, taking an example for syntax A and E

Example :1     Always @ ( x,y,z)
     Begin
         Sum = x + y + z
     End

 

Point B, C and D are normally used for sequential logic implementation

Example : 2

     always @ ( posedge clock or negedge reset )
     begin
     if (!reset)
         q<= 0;
     else
         q<= data
     end

Point F and G are equivalent in behavior. These are some easy options to use without bothering about the sensitivity list

Example : 3     Always @ (*)
     Begin
         Sum = x + y + z
     End

 

In this case whatever values are used in the right hand side (RHS) would be taken in the sensitivity list So there is any change in the x , y or z values, the always block would be executed..
 

 

 

 

Posted in VERILOG | Tagged: , , , | 2 Comments »

What is a module in verilog?

Posted by Nityanand Dubey on July 20, 2008

We can assume that a design is made of different modules/blocks.
 
  As a definition we can say
 
  “A module is a block with well defined inputs, outputs and interconnections (functionality)”
 
  The module is defined by keyword “module” and ends with endmodule Here is an example of module for a full adder
 
 
module adder (co, sum, x, y, cin);
  output co;
  output sum;
  input x;
  input y;
  input cin;
 
  reg co;
  reg sum;
  always @(*)
  {co, sum} = x + y + cin;
  endmodule
 

 
  In this example – module is a keyword to define the bock named “adder”
 
  All the inputs and outputs of block are defined within the ( …. ) and the block ends with “endmodule” statement
 
  Inside the block there is description of each I/O whether they are inputs or outputs. Functionality of adder is also given with the always statement. .

Posted in VERILOG | Tagged: , , | Leave a Comment »

What is the difference between signals and variables

Posted by Nityanand Dubey on July 7, 2008

There are three major difference between a signal and a variable in the VHDL

 Coverage wise –

Signals has coverage to whole architecture, it can be access from any place in a Architecture of entity

A variable is local to a procedure defined in the architecture

Behavior wise

Signal assignments executes concurrently, It means, if we have 5 signals assignment, then it depends on the simulator to decide which signal to be assigned first

In case of variable, it takes the value immediately OR in other language, it executes sequentially

Synthesis Wise –

If we have 2 variable and two signals used in a process, the variables infer just a wire during synthesis, but the signals infer a Flop.

 Also you can say that – the number of flops inferred by a process is roughly equal to the number of signals used in it (in Left had side)

 

 

 

 

 

Posted in VHDL | Tagged: , , , , , | 1 Comment »

What is Gate ( Logic Gates )

Posted by Nityanand Dubey on July 7, 2008

In normal language, Gate donates “entry” or door. By relating this thing – Logic “Gates” are nothing but the door of “Digital Electronics”. So anybody who wants to learn Digital, must need to cross the entry point, called Gate-

 

 

 

Posted in Layman's Electronincs | Leave a Comment »

What is the difference between a function and a task?

Posted by Nityanand Dubey on July 6, 2008

  1. behavior

Function : function call happens in real time OR no simulation delay can be inserted during the function call

Task : Tasks can be inserted with a delay

  1. No of outputs :

Function : A function can have at least one input arg to be passed, and also it can have only one output to drive

Task : Task can have any no of inputs and outputs.

  1. Nesting :

Function : A function can call a function inside it but not a task

Task : Task can call either a function or a task inside it.

  1. Synthesis :

Function : A function can be synthesized

Task : Tasks are not synthesizable

  1. Limitations :

Function : A function does not allow any delay, timing, event inside it

Task : Tasks can have delays, events inside it

  1. Usage :

Function : A can be used for RTL as well as behavioral coding ( mostly for combinational logic)

Task : Tasks can be used for behavioral modeling only.

Posted in VERILOG | Tagged: , , , , | Leave a Comment »

What is the difference between blocking and nonblocking statements in verilog

Posted by Nityanand Dubey on July 6, 2008

In verilog, we have two types of assignment operators i.e. blocking (=) and non- blocking (<=). These two have theirs special usages – Here are the differences

1. behavior  –

The blocking statements are as similar as any sequential programming language. In short, they execute sequentially.

The non-blocking statements are executed concurrently; it means if five statements are written together then it would depend on the simulator to execute which statement first. Ideally all the statements should execute at the same time.

  1. Synthesis –

The blocking statements infer simple “connection OR wire” during the synthesis,

Non-blocking statements infer Flop/latch.

  1. Usage

The blocking statements are used normally for combinational logic implementation OR whenever the synchronization/sequence required between the assignments,

Non blocking statements are used for sequential implementation

Posted in VERILOG | Tagged: , , , , , | Leave a Comment »