Nityanand's Weblog

  • view my stats

    free page hit counter
  • Earn Money by viewing ads

  • Useful Links

Archive for August, 2008

What is the difference between a Latch and a Flip-Flop

Posted by Nityanand Dubey on August 21, 2008

 

The Latches and Flop-flop, both are considered as a sequential element of Digital Design. It means the output of both blocks; depend on the input as well as the previous output.

Here are some difference between the latches and Flip-flops(FF)

1. Functionality : The Latches are level sensitive blocks, it means the output may change any time during the active phase of clock ( As input changes) In other hand the Flip-flops as edge sensitive and output changes only with the clock edge. In between it does not changes (even though input toggles)

2.  Area : The latches take less area than Flip-flops, Since the Flip-flops made of latches. The D Flip flop made of two latches in master-slave configuration.

3.  Speed: The latches are more faster than then the Flop flops, Since less number of gates used in the latches,

4. . Clock : Latches may of may not have clocks. But A Flip-flop must be having a clock.

Posted in Digital Design | Tagged: , , , , | 1 Comment »

What are sequential and parallel blocks, what is fork and join statements? How it is deffer than begin and end?

Posted by Nityanand Dubey on August 2, 2008

 In verilog, we have two types of block – sequential blocks and parallel blocks. Lets look into both blocks one by one

1. Sequential Blocks –

In the sequential blocks, begin and end keywords are used to group the statements, All the statement in this group executes sequentially. ( this rule is not applicable for nonblocking assignments). If the statements are given with some timing/delays then the given delays get added into. It would be clearer with following examples.

Example -1 –

reg a,b,c;
initial
begin
     a = 1′b1;
     b = 1′b0;
     c = 1′b1;
end
The Example -1 is showing the sequential block without delays, All the statements written inside the begin-end will execute sequentially and after the execution of initial block, final values are a=1, b=0 and c=1

Example -2 –

reg a,b,c;
initial
begin
     #5 a = 1′b1;
     #10 b = 1′b0;
     #15 c = 1′b1;
end

The Example -2 is showing the sequential block with delays, In this case, the same statements are given with some delays, Since All the statements execute sequentially, the a will get value 1 after 5 time unit, b gets value after 15 time unit and c will take value 1 after 30 time unit

2. parallel Blocks –

The statements written inside the parallel block, execute parallel, If the sequencing is required then it can be given by providing some delays before the statements. In parallel blocks, all the statements occur within fork and join

Example -3 –

reg a,b,c;
initial
fork
     #5 a = 1′b1;
     #10 b = 1′b0;
     #15 c = 1′b1;
join

Form Example -3, all the statements written inside the fork and join, executes parallel, it means the c with have value ‘1′ after 15 time unit, in case of sequential blocks it was 30 time unit ( example 2)

The fork and join statements can be nested with begin-end

Example -4 ( Nested block)

reg a,b,c,d;
initial
begin
fork
     #5 a = 1′b1;
     #10 b = 1′b0;
     #15 c = 1′b1;
join

  1. 30 d = 1′b0;

end

From Example -4, the initial block contains begin-end and fork-join both. In this case c takes value after 15 time unit, and d takes the value after 30 time unit.

 

Posted in VERILOG | Tagged: , , , , , , , , | Leave a Comment »