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Archive for December, 2008

Vital Table Symbols for VHDL designs

Posted by Nityanand Dubey on December 9, 2008

During working with some vital designs, initially I felt many difficulties to understand the symbols used in the Vital State Table.

This vital table is refered from IEEE – VITAL ASIC modeling Specification –

Type VitalTableSymbolType is {

‘/’ — 0->1

‘’ — 1->0

‘P’ Union of ‘/’ and ‘^’ ( any edge to 1)

‘N’ Union of ‘’ and ‘v’ ( any edge to 0)

‘r’ — 0->X

‘f’ — 1->X

‘p’ Union of ‘/’ and ‘r’ ( any edge from 0)

‘n’ Union of ‘’ and ‘f’ ( any edge from 1)

‘R’ Union of ‘^’ and ‘p’ ( any possible rising edge)

‘F’ Union of ‘v’ and ‘n’ ( any possible falling edge)

‘^’ X->1

‘v’ — X->0

‘E’ Union of ‘v’ and ‘^’ ( any edge from X)

‘A’ Union of ‘r’ and ‘^’ ( rising edge to or from X)

‘D’ Union of ‘f’ and ‘v’ ( falling edge to or from X)

‘*’ Union of ‘R’ and ‘F’ ( any edge)

‘X’ — Unknown Level

‘0’ Low Level

‘1’ High Level

‘-’ Don’t Care

‘B’ 0 or 1

‘Z’ High Impedance

‘S’ Steady Value

};

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