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Archive for March, 2009

Design synthesis and relevant verilog code for DFF

Posted by Nityanand Dubey on March 31, 2009

For RTL Coding, one should know that what code will infer which hardware in the design and vise versa.

The Design engineer should be aware of relevant code and the output logic so he can be able to minimize the design and the no of gates using.

In this post we will see deferent DFF and their verilog codes

DFF ( D- Flip-Flop)

reg q;

always @ (posedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the posegde of the clock and it will remain untouched till next posedge of the clock since the q is defined as reg.

D-Flip Flop

D-Flip Flop

DFF ( D- Flip-Flop) with Asynchronous reset.

reg q;

always @ (posedge clk or posedge reset)
if (reset)
q <= 1’b0;
else
q <= d;

According to above code, the reset is positive edge triggered and asynchronous so it is kept in the sensitivity list of always block with the posedge.

Inside the always block, there are a conditional statement to check whether the reset is true (1), otherwise it behaves as normal DFF

DFF - Async Reset

DFF - Async Reset

DFF ( D- Flip-Flop) with synchronous reset

reg q;

always @ (posedge clk)
if (reset)
q <= 1’b0;
else
q <= d;

Synchronous reset means the flop will be reset only with the posedge of clock, hence the sensitivity list does not have the reset signal; However it check the reset for true whenever the posedg of clock comes.

DFF - Sync Reset

DFF - Sync Reset

DFF ( D- Flip-Flop) with gated clock.

reg q;
wire gtd_clk = enable && clk;

always @ (posedge gtd_clk)
q <= d;

Many times it becomes required to apply clock to the design only when the enable is active. This is done by the gated clock. The clock and enable both are the inputs to a and gate and the output of the gate goes to the clock input of the flop.

DFF - Gated Clock

DFF - Gated Clock

Data Enabled DFF

reg q;

always @ (posedge clk)
if (enable)
q <= d;

Data Enabled flops has a mux at the data input, which is controlled by the enable signal. Now even the posedge of clock comes to the flop, flop will not change the value until enable is not active.

DFF - Data Enable

DFF - Data Enable

Negative Edge triggered DFF

reg q;

always @ (negedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the negedge of the clock and it will remain untouched till next negedge of the clock since the q is defined as reg.

DFF -Negative Edge

DFF -Negative Edge



Posted in ASIC Design Flow, VERILOG | Tagged: , , , , , , | Leave a Comment »

What is Timescale in verilog codes

Posted by Nityanand Dubey on March 18, 2009

The ‘timescale is one of the compiler directive to specify the unit for the delays used in the design with their precision.

The timescale line is very important in the verilog simulation, because there are no any default delays specified by the verilog.

Syntax :

`timescale <time unit>/<time precision>

Here :

time unit : This is the time to be used as one unit for all the delays used in the design.

time precision : This represents the minimum delay which needs to be considered during simulation or it decides that how many decimal point would be used with the time unit.

Range of Timescale :

The range for time unit can be from seconds to femto-seconds, which includes all the time units including s (second), ms(mili-second), us(micro-second), ns(nano-second), ps(pico-second) and fs(femto-second).

Example :

`timescale 1ns/1ps

Here :

1ps = 0.001 ns

#1; // = 1ns delay

#1.003; // = will be considered as a valid delay

#1.0009; // = will be taken as 1 ns only since it is out of the precision value.

Posted in VERILOG | Tagged: , , , | 3 Comments »

What is the Threshold Voltage in the MOS Transistors

Posted by Nityanand Dubey on March 16, 2009

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

In this chapter, we will not take the help of electronic symbols, instead of that, we will relate this phenomenon with a very common example from our daily life.

To understand the concept of threshold voltage, Lets See the following Image .

Image Threshold

An Example of theshold

An Example of theshold

Now in the diagram –

We have a tap fitted tank. the water can be filled inside the tank from the top of the tank, and the water can be taken out from the tap.

Now, The water can not be taken out from the tap until the water level touches the tap level

Lets relate the amount of required water to get the tap level is the threshold voltage and the amount of water taken out from the tap is the output voltage. The output water from the tank will not be equal to the incoming water, It will always be less than the threshold amount of water

Summary : The Threshold voltage is the critical voltage point, after this voltage the actual operation of MOS Starts the output voltage will be always less than the threshold voltage in the total applied voltage.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , | Leave a Comment »

What is the Kirchhoff’s current Law?

Posted by Nityanand Dubey on March 13, 2009

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept.

To understand the Kirchhoff’s Law, Lets take an example of Water supply line

Refer the diagram given bellow

Image Kirchaff’s law

An Example of kirchoff's Law

An Example of kirchoff's Law

Now from the diagram –

Here A, B, C and F are the four pipe lines those are bringing water to the point and D and E are the two pipe lines those are taking the water away from the point.

From the figure, It is clear that the total amount of input water will be equal to the total amount of output water.

One more thing is clear from given example, that the pipe line D is wider than pipe E Which clearly means that, the amount of water carrying by this line would be more than the any other.

So you can clearly say that the wider current carrier ( thicker wire) would carry more current than thinner wires

Summary : The Total outgoing Current at the any point of circuit is equal to total incoming current at the point. Also the wider wires would carry more current than the thinner wires

Mathematical Proof : By Puneet Arora

If A, B, C and F are carrying currents
I1, I2, I3 and I4 respecively

and currents carried by D and E are I5 and I6 repectively

then according to KIRCHHOFF’s LAW

I1 + I2 + I3 + I4 = I5 + I6

Resitance offered by a wire to the current flowing though it

R =pl/A

where p = resistivity of the wire.
It depends upon the material used for making the wire
l = length of the wire
A = Area of cross section of wire.

It supports that a shorter and wider wire
will offer lesser resistance
as compared to a longer and thin wire.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , | Leave a Comment »

How does the diod work as a Switch?

Posted by Nityanand Dubey on March 9, 2009

-Concept By Bhuvan Plaha .

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

To remember this Concept, Lets assume the electronic symbol of a Diode and a switch The Symbol of diode looks like a arrow which can be used as a …….

Now, Lets See the following Image .

Image Diode – GO

Diode : Follow direction and go

Diode : Follow direction and go

Now according to the diagram –

The diode symbol shows the direction to go. In the middle of way, there is a inclined path, and at the top, you need to jump and go further. Remember this figure as a diode in forward bias.

Now Lets see the next diagram, which describes the behavior of diod in reverse bias

Image Diod Oh !!!

Diode : No Way !!!

Diode : No Way !!!

Now by looking into the image , It is clear that when it is tried to come by the same path, the obstacle could not be crossed and nothing will appear it the left hand side.

Summary : The Diode lets the current go in Forward Bias But blocks in the Reverse Bias. and it works as a Switch

Mathematical Proof : COMING SOON …..

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , , | 1 Comment »

What is a Universal Gate and Why NAND is called a Universal gate?

Posted by Nityanand Dubey on March 6, 2009

A Logic Gate which can infer any of the gate among Logic Gates. OR a gate which can be use to create any Logic gate is called Universal Gate

We have following Logic Gates

NOT
AND
OR
NAND
NOR
XOR
XNOR

NAND and NOR Gates are called Universal Gates because all the other gates can be created by using these gates

In this post, we will see to how to make all other logic gates by using the NAND Gate

1. NAND gate to NOT Gate conversion

Refer the following diagram –

Digital : Image – NAND to NOT

Nand to Not conversion

Nand to Not conversion

Here the same input is applied to the both inputs of a NAND Gate

According to NAND Gate – If A and B are two inputs than output equation will be (A.B)’

For this case :

= (X.X)’
= X’

2. NAND Gate to AND Gate Convertion

Refer following diagram for NAND to and Gate conversion –

Digital : Image – NAND to AND

NAND to AND conversion

NAND to AND conversion

For this case – x and y are the two inputs to a NAND gate and the output of the First NAND gate goes again to an another NAND gate’s inputs.

=> s1 = (X.Y)’
=> s2 = (s1.s1)’ = s1’
=> s2 = ((X.Y)’)’
=> X.Y

3. NAND Gate to OR Gate Conversion

Refer the following Diagram

Digital : Image – NAND to OR

NAND to OR Conversion

NAND to OR Conversion

According to diagram –

s1 = (X.X)’ = X’
s2 = (Y.Y)’ = Y’
s3= (s1.s2)’ = (X’.Y’)’
=> (X’)’ + (Y’)’
=> X+Y

4. NAND Gate to NOR Gate Convertion

Refer the following Diagram

Digital : Image – NAND to NOR

NAND to NOR conversion

NAND to NOR conversion

According to diagram –

s1 = (X.X)’ = X’
s2 = (Y.Y)’ = Y’
s3= (s1.s2)’ = (X’.Y’)’
=> (X’)’ + (Y’)’
=> X+Y
s4 = (s3.s3)’ = s3’
=> (X + Y)’

5. NAND to XOR Gate

Digital : Image – 5

6. NAND to XNOR Gate

Digital : Image – 6



Posted in Digital Design | Tagged: , , , , , , , , , , , | 8 Comments »

What is the effect of AC and DC current with an inductor?

Posted by Nityanand Dubey on March 5, 2009


Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

Same as last chapter, to understand the behavior of a inductor with the AC and DC currents, we will take the help of the electronic symbols used for inductor, AC current and DC current .

To understand the effect of a inductor with the DC current, Lets See the following Image .

Image Inductor with DC

Inductor with DC

Inductor with DC

Now according to the diagram –

DC Waves are straight waves So they can easily pass through the tunnel built in the inductor

Now Lets see the next diagram, which describes the behavior of AC Current with the inductors

Image Inductor with AC

Inductor with AC

Inductor with AC

Now by looking into the image , It is clear that AC current tries to go though the Inductor but due to its specific structure, is scrambles with the inductor and could not pass through

So we can say that an inductor resists the AC current

Summary : The Inductor Blocks the AC Current but allows the DC current to pass though it

Mathematical Proof : By Puneet Arora

Resistance offered by an Inductor to a signal flowing through it:

R = 2πfl

where f = frequecy of the signal
l = value of the inductor

For a DC signal,

DC signal does not vary its value as an AC signal does.
Therefore, frequency of a DC signal,

f = 0HZ

This makes Inductor resistance R = 2πfl ~ zero

This makes it clear that an inductor offers no resistance to a DC signal.

FOR AN AC signal

AC signal is a time varying signal and attains positive and negative values periodically or non periodically. So it has a finite value of frequncy say f

Therefore resistance offered by an inductor to an AC signal

R = 2πfl = A finite value depending upon frequcncy of the AC signal.

Higher the frequecy of the AC signal, higher is the resistance offered.
So an inductor blocks high frequecy AC signals.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , , | Leave a Comment »

What is the effect of AC and DC current with a capacitor?

Posted by Nityanand Dubey on March 3, 2009

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

To understand the behavior of a capacitor with the AC and DC current, we will Take the help of the Capacitor Symbol and the symbol of AC and DC currents.

Lets See the following Image .

Image Layman’s : 1

Ac on cap

Ac on cap

Now according to the diagram –

AC Waves can pass through the Capacitor because of its Specific Shape

Now Lets see the next diagram, which describes the behavior of DC Current with the capacitor

Image Layman’s : 2

DC on cap

DC on cap

Now According to the image, It is clear that DC current tries to go though the capacitor but is just crashes down by the Capacitor’s huge wall

So we can say that a capacitor breaks the DC Current

Summary : The Capacitor Blocks the DC Current but allows the AC current to pass though it

Mathematical Proof : By Puneet Arora

RESISTANCE OFFERED BY A CAPACITOR TO A SIGNAL FLOWING THROUGH IT:

R = 1/2πfc
where f = frequency of the signal
c = value of the capacitor

FOR A DC SIGNAL

DC signal does not vary its value as an AC signal does.
Therefore, frequency of a DC signal,

f = 0HZ

This makes Capacitor resistance R = 1/2πfc ~ infinite

This makes it clear that a capacitor blocks a DC signal.

FOR AN AC signal

AC signal is a time varying signal and attain positive and negative values periodically or non periodically. So it has a finite value of frequncy say f

Therefore resistance offered by a capacitor to an AC signal

R = 1/2πfc = A finite value depending upon frequcncy of the AC signal.

For higher frequency signal, resistance offered is very small.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , , | 2 Comments »