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Using event based modeling in verilog to avoid Racing between always blocks.

Posted by Nityanand Dubey on November 28, 2009


In most of our designs, we have to perform some operation on the posedge of clock. To implement this, we normally use different always block with the posedge of clock in the sensitivity list.

Some times, we need to use the signal in one always block, which is getting assigned a value from another, and here the actual problem starts.

Since the all the always blocks execute concurrently in the design, which may create racing between signals, which is again varies among simulator to simulator.

For this scenario, the signals may get value from one always block before/after it is used in another one.

Using “event” in the verilog programming can be one way to take care this kind of situation.

Example 1 :

Here two always blocks are shown,

In this case we are trying to set some modes by looking into some conditions. Also, we want to use the modes at the posedge of clock and perform some other operation.

Since both always blockes are working at the same posedge of clock, which may create a racing between the mode signals.

This is a small example but in real-time scenario, it might be more complex and big.

It may take the new value of mode of continue with the older value, depends on the simulator’s algorithm.

Block – 1 :

always (posedge clock)
begin
    if (condition1)
        mode1 = 1’b1;
    else if (condition2)
        mode2 = 1’b1;
    else
        mode3 = 1’b0;
end

Block – 2 :

always (posedge clock)
begin
    if( mode1 && conditions3)
        output <= input1;
    else if (mode2 && condition4)
        output <= input2
    else
        output <= 2’b0;
end

Now, Lets try to avoid the racing between these two always blocks.

Here, we use an “event” to trigger the other always block, and the triggering will take place at the last of first always block.

Since we wanted to run the both always block at the posedge of the clock, which is also happening here.

By using the event in the sensitivity list of other always block makes sure that this block will execute when the first will be completed, and it will be able to use the new values assigned to the mode variables.

We can have multiple events in the design.

// event declaration
event ev_mode

Block – 1 :

always (posedge clock)
begin
    if (condition1)
        mode1 = 1’b1;
    else if (condition2)
        mode2 = 1’b1;
    else
        mode3 = 1’b0;
    -> ev_mode
end

Block – 2 :

always (ev_mode)
begin
    if( mode1 && conditions3)
        output <= input1;
    else if (mode2 && condition4)
        output <= input2
    else
        output <= 2’b0;
end

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One Response to “Using event based modeling in verilog to avoid Racing between always blocks.”

  1. dwieberd said

    I think you can accomplish the same thing (avoiding races in simulation) by simply using Verilog’s non-blocking assignment operator (<=) instead of the blocking version (=) for all registered logic blocks. This forces the signals to behave more like real hardware, with signal assignments not taking place until some time after the clock edge (ie. it gives them hold time).

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