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Archive for the ‘ASIC Design Flow’ Category

How to pass parameters/generic values from the simulator’s command line

Posted by Nityanand Dubey on February 13, 2012

** Note: We have used common term parameters applicable for verilog designs. In VHDL the ‘Generics’ are used for the same.

We use different parameters/generics in the verilog/vhdl designs. Parameters give us huge re-usability of the codes. It means we can use same module/code various times in a big design and each time it’s behavior can be different.

For Example: If I have a parameterized module of a memory instance, where we can configure the length/width of the array by passing the number of words and number of bits through parameters, then we can use same code in various places of a design wherever the memory is needed and the configuration of the instance can be controlled by parameters.

Now, since we have only one module/code which is being used by all the other similar memory instances but different configuration

In the module/code, we provide some default values to the parameter. We need to overwrite the default parameters with the relevant values, If we want to use the module with various configurations,.

Here are the option used by different commonly used industry simulators (VCS, NC-Verilog and ModelSim)

ModelSim: The Parameters value can be passed with ‘vsim’ command in the ModelSim simulator

Assuming we want to supply a parameter value globally to all the modules


Example:  All the parameters present in the models named as “simulation_mode” should be active


Here: “yes” is the value of simulation_mode  to make it as active.

 VCS –

For VCS, Let’s consider another example, say, I want memory ‘A’ with width of 16 bit and Memory ‘B’ width as 64

-pvalue+top/mem_A/No_of_bits=16  -pvalue+top/mem_B/No_of_bits=64

NC-Verilog: To perform same thing the ncverilog uses “defparam” syntax, let’s follow same example as we did in case of VCS –

If you are using 3 step NC-verilog command then following syntax will be used with “ncelab” command line.

Ncelab  […. Other options] -defparam  top.mem_A.No_of_bits=16  -defparam  top.mem_B.No_of_bits=64 

If you are using single step NC-Verilog command then the syntax will look like –

ncverilog [… other options …] +defparam+ top.mem_A.No_of_bits=16

Posted in ASIC Design Flow | Tagged: , , , , , , , , , , , , , | Leave a Comment »

Frequently used CVS Commands

Posted by Nityanand Dubey on November 29, 2010

What is a Version control System?

In simple language, version control system is a database, which stores all the change records of your work. With the help of a version control system, you can make sync in a project while working in a team, whatever change is made by one team member is updated to a common database with the changes/comment/author’s name and the same can be accessed by other peoples whenever is required.

What is CVS?

The CVS (Concurrent Versions System) is a commonly used version control system among the software developers. It gives ease to work on same project by several users. Version control system software keeps track of all work and all changes in a set of files.

Frequently used commands in CVS

Here are some frequently used steps and relevant commands. Before using these commands, make sure the CVS is configured in your working environment and cvsroot is pointing to a desired location.

1. Add a new directory/file in the CVS Database:

cvs add <filename>

This command adds a desired “filename” in the CVS database. Note that this command adds only the file name. To update the file in the database, you need to use the check-in command (described in next point).

This command is used only once with a file/directory at first time.

 2. Checking -in a file into CVS database:

After adding a filename, we need to put the whole file into the database using following commands.

cvs checkin -m “” <filename>


cvs ci -m “” <filename>


cvs commit -m “” <filename>

Here :

 -m : is a message option to specify any short information about the change You can check in as many as versions of a file and each check in gives you a specific version No of the file

3. Checking out a file from CVS Database

cvs checkout “filename”


cvs co “filename”

Here the filename can be a file or a directory.

The above command brings the latest available version of the given filename. The “filename” may ask to contain relative the path of the cvs directory structure.

4. Checking out a specific version of file.

If you want to get a specific version of file, please use following command –

cvs co -r <version> <file name>

5. Updating the files from database to your environment

This feature works same as CVS checkout. There are some minor changes than the checkout command.

Following command brings the required file(s) which are updated in the CVS but not synced with your environment.

cvs update < filename>


 cvs up <filename>

 6. Tagging a file:

Tagging is a very useful feature given in the version control system. Suppose, you have achieved an intermediate milestone of a project and you have different files with different versions in the CVS database. Now you want to freeze them for the milestone, then you need to use a tag for them.

You can provide a same tag to all the relevant files from different versions and you can get them anytime by supplying the tag Info.

cvs tag <filename>

You can also use the wildcard characters for any of the cvs application.

7. Checking out a set of file from a given tag.

 Now you want to bring all the files of the given tag.

cvs co -r <filename>

 8. Deleting a tag :

 Following command is used to delete a tag info from a file.

cvs ratg -d <tagname> <filename>

9. Creating a copy of the tag :

 cvs rtag -r <current tag> <new tag> <filename>

10. Retagging of a file .

 Let say after tagging of a set of files, you see an urgent change required in one of the file and you do not want to give any other tag name (due to any reason) for this small change. Then you need to retag the file. Please follow following steps.

A. copy the tag to an another temporary tag (this is required for records that the tag was changed)

cvs rtag -r <current tag> <new tag> <filename>

B. delete the current tag (This is required because you can not give a tag name which is already exists.)

cvs ratg -d  <tag name> <filename>

C.Tag the file with a tagname

cvs tag <tagname> < filename>

11. Finding difference between files from two different versions

 To see the difference in the files form two deferent cvs version can be seen by –

cvs diff -r <version1> -r <version2> <filename>

12. View CVS version information.

The see the log messages, which was given at the time of check in with -m option can be seen by

 cvs log <filename>

To see the status of the file, whether is in sync with the database file of locally modified can be seen using –

cvs status <filename>

To view the tag information with the status use following command

cvs status -v <filename>

Posted in ASIC Design Flow, SHELL | Tagged: , , | 1 Comment »

Design synthesis and relevant verilog code for DFF

Posted by Nityanand Dubey on March 31, 2009

For RTL Coding, one should know that what code will infer which hardware in the design and vise versa.

The Design engineer should be aware of relevant code and the output logic so he can be able to minimize the design and the no of gates using.

In this post we will see deferent DFF and their verilog codes

DFF ( D- Flip-Flop)

reg q;

always @ (posedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the posegde of the clock and it will remain untouched till next posedge of the clock since the q is defined as reg.

D-Flip Flop

D-Flip Flop

DFF ( D- Flip-Flop) with Asynchronous reset.

reg q;

always @ (posedge clk or posedge reset)
if (reset)
q <= 1’b0;
q <= d;

According to above code, the reset is positive edge triggered and asynchronous so it is kept in the sensitivity list of always block with the posedge.

Inside the always block, there are a conditional statement to check whether the reset is true (1), otherwise it behaves as normal DFF

DFF - Async Reset

DFF - Async Reset

DFF ( D- Flip-Flop) with synchronous reset

reg q;

always @ (posedge clk)
if (reset)
q <= 1’b0;
q <= d;

Synchronous reset means the flop will be reset only with the posedge of clock, hence the sensitivity list does not have the reset signal; However it check the reset for true whenever the posedg of clock comes.

DFF - Sync Reset

DFF - Sync Reset

DFF ( D- Flip-Flop) with gated clock.

reg q;
wire gtd_clk = enable && clk;

always @ (posedge gtd_clk)
q <= d;

Many times it becomes required to apply clock to the design only when the enable is active. This is done by the gated clock. The clock and enable both are the inputs to a and gate and the output of the gate goes to the clock input of the flop.

DFF - Gated Clock

DFF - Gated Clock

Data Enabled DFF

reg q;

always @ (posedge clk)
if (enable)
q <= d;

Data Enabled flops has a mux at the data input, which is controlled by the enable signal. Now even the posedge of clock comes to the flop, flop will not change the value until enable is not active.

DFF - Data Enable

DFF - Data Enable

Negative Edge triggered DFF

reg q;

always @ (negedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the negedge of the clock and it will remain untouched till next negedge of the clock since the q is defined as reg.

DFF -Negative Edge

DFF -Negative Edge

Posted in ASIC Design Flow, VERILOG | Tagged: , , , , , , | Leave a Comment »

Vital Table Symbols for VHDL designs

Posted by Nityanand Dubey on December 9, 2008

During working with some vital designs, initially I felt many difficulties to understand the symbols used in the Vital State Table.

This vital table is refered from IEEE – VITAL ASIC modeling Specification –

Type VitalTableSymbolType is {

‘/’ — 0->1

‘’ — 1->0

‘P’ Union of ‘/’ and ‘^’ ( any edge to 1)

‘N’ Union of ‘’ and ‘v’ ( any edge to 0)

‘r’ — 0->X

‘f’ — 1->X

‘p’ Union of ‘/’ and ‘r’ ( any edge from 0)

‘n’ Union of ‘’ and ‘f’ ( any edge from 1)

‘R’ Union of ‘^’ and ‘p’ ( any possible rising edge)

‘F’ Union of ‘v’ and ‘n’ ( any possible falling edge)

‘^’ X->1

‘v’ — X->0

‘E’ Union of ‘v’ and ‘^’ ( any edge from X)

‘A’ Union of ‘r’ and ‘^’ ( rising edge to or from X)

‘D’ Union of ‘f’ and ‘v’ ( falling edge to or from X)

‘*’ Union of ‘R’ and ‘F’ ( any edge)

‘X’ — Unknown Level

‘0’ Low Level

‘1’ High Level

‘-’ Don’t Care

‘B’ 0 or 1

‘Z’ High Impedance

‘S’ Steady Value


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How can we take help from Front-End Simulators like ncverilog, modelsim, vcs etc.

Posted by Nityanand Dubey on October 10, 2008

Each EDA Tool assigns a warning or a error as it finds anything abnormal in the written code and due to severity of the warning/Error, it decides to proceed further or not.

Many times, the tool given messages are not comprehensive and user needs to know some more details about the reason of failures.

Here are some tool help techniques to find the help about the respective Error/warning/messages

  1. Simulator : NC-Verilog

NC-Verilog is a simulator provided by Cadence design system. It is a part of IUS package offered by the cadence. There is a utility (executable) present in this package in terms of providing quick details of messages. This utility is called “nchelp”

This executable path should be present in your executable path list. It can be checked with the “which” command

> which nchelp


If the utility is not in the path list, Either you can add it or also you can use the executable with the complete path (from installation area)

Usage :

> nchelp [options] tool error

Example :

Here is an example of error message –

ncelab: *W,SBNGL2 (./dut.v,1366|11): The sum of both limits in $setuphold or $recrem is less than the tolerance value: the negative limit will be set to zero.

Now If user wants to see the description of the error –

Ø nchelp ncelab SBNGL2

Here – ncelab is the utility for elaboration used by nc-verilog simulator

SBNGL2 – the Error Code

Output from this command –

nchelp: 08.10-s005: (c) Copyright 1995-2008 Cadence Design Systems, Inc.

ncelab/SBNGL2 =

The magnitude of the negative limit value minus the positive limit value in a $setuphold or $recrem timing check must be less than or equal to the tolerance value given by -ntc_tolerance option (by default, the tolerance value is 0).

The limits will be adjusted: by default, the negative limit will bet set to 0. However, if -ntc_neglim is specified, the negative limit will be adjusted to match the positive limit; if the -ntc_poslim is specified, the positive limit will be adjusted to match the negative value.

  1. Simulator : ModelSim

In ModelSim Simulator, It assigns an message number with all the messages. To get the details of the specific warning/error, User needs to use the associated number.

To provide help for debugging, ModelSim provides a Utility called “verror”

First User needs to be sure that the executable path is present in the global path list. This can be checked as

Ø which verror

This should show a valid path of executable “verror”

Now, User needs to write the Error number with this command

Syntax :

verror < message id>


> veeror 3035

Output :

vsim Message # 3035:

This warning occurs when the level of an instantiation reaches a certain depth. It indicates that the instantiation might be recursive. A further attempt is made to complete the instantiation. If the maximum depth is reached then an elaboration error is generated.

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