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What is the Threshold Voltage in the MOS Transistors

Posted by Nityanand Dubey on March 16, 2009

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

In this chapter, we will not take the help of electronic symbols, instead of that, we will relate this phenomenon with a very common example from our daily life.

To understand the concept of threshold voltage, Lets See the following Image .

Image Threshold

An Example of theshold

An Example of theshold

Now in the diagram –

We have a tap fitted tank. the water can be filled inside the tank from the top of the tank, and the water can be taken out from the tap.

Now, The water can not be taken out from the tap until the water level touches the tap level

Lets relate the amount of required water to get the tap level is the threshold voltage and the amount of water taken out from the tap is the output voltage. The output water from the tank will not be equal to the incoming water, It will always be less than the threshold amount of water

Summary : The Threshold voltage is the critical voltage point, after this voltage the actual operation of MOS Starts the output voltage will be always less than the threshold voltage in the total applied voltage.

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Posted in Layman's Electronincs | Tagged: , , | Leave a Comment »

What is the Kirchhoff’s current Law?

Posted by Nityanand Dubey on March 13, 2009

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept.

To understand the Kirchhoff’s Law, Lets take an example of Water supply line

Refer the diagram given bellow

Image Kirchaff’s law

An Example of kirchoff's Law

An Example of kirchoff's Law

Now from the diagram –

Here A, B, C and F are the four pipe lines those are bringing water to the point and D and E are the two pipe lines those are taking the water away from the point.

From the figure, It is clear that the total amount of input water will be equal to the total amount of output water.

One more thing is clear from given example, that the pipe line D is wider than pipe E Which clearly means that, the amount of water carrying by this line would be more than the any other.

So you can clearly say that the wider current carrier ( thicker wire) would carry more current than thinner wires

Summary : The Total outgoing Current at the any point of circuit is equal to total incoming current at the point. Also the wider wires would carry more current than the thinner wires

Mathematical Proof : By Puneet Arora

If A, B, C and F are carrying currents
I1, I2, I3 and I4 respecively

and currents carried by D and E are I5 and I6 repectively

then according to KIRCHHOFF’s LAW

I1 + I2 + I3 + I4 = I5 + I6

Resitance offered by a wire to the current flowing though it

R =pl/A

where p = resistivity of the wire.
It depends upon the material used for making the wire
l = length of the wire
A = Area of cross section of wire.

It supports that a shorter and wider wire
will offer lesser resistance
as compared to a longer and thin wire.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , | Leave a Comment »

How does the diod work as a Switch?

Posted by Nityanand Dubey on March 9, 2009

-Concept By Bhuvan Plaha .

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

To remember this Concept, Lets assume the electronic symbol of a Diode and a switch The Symbol of diode looks like a arrow which can be used as a …….

Now, Lets See the following Image .

Image Diode – GO

Diode : Follow direction and go

Diode : Follow direction and go

Now according to the diagram –

The diode symbol shows the direction to go. In the middle of way, there is a inclined path, and at the top, you need to jump and go further. Remember this figure as a diode in forward bias.

Now Lets see the next diagram, which describes the behavior of diod in reverse bias

Image Diod Oh !!!

Diode : No Way !!!

Diode : No Way !!!

Now by looking into the image , It is clear that when it is tried to come by the same path, the obstacle could not be crossed and nothing will appear it the left hand side.

Summary : The Diode lets the current go in Forward Bias But blocks in the Reverse Bias. and it works as a Switch

Mathematical Proof : COMING SOON …..

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Posted in Layman's Electronincs | Tagged: , , , | 1 Comment »

What is a Universal Gate and Why NAND is called a Universal gate?

Posted by Nityanand Dubey on March 6, 2009

A Logic Gate which can infer any of the gate among Logic Gates. OR a gate which can be use to create any Logic gate is called Universal Gate

We have following Logic Gates

NOT
AND
OR
NAND
NOR
XOR
XNOR

NAND and NOR Gates are called Universal Gates because all the other gates can be created by using these gates

In this post, we will see to how to make all other logic gates by using the NAND Gate

1. NAND gate to NOT Gate conversion

Refer the following diagram –

Digital : Image – NAND to NOT

Nand to Not conversion

Nand to Not conversion

Here the same input is applied to the both inputs of a NAND Gate

According to NAND Gate – If A and B are two inputs than output equation will be (A.B)’

For this case :

= (X.X)’
= X’

2. NAND Gate to AND Gate Convertion

Refer following diagram for NAND to and Gate conversion –

Digital : Image – NAND to AND

NAND to AND conversion

NAND to AND conversion

For this case – x and y are the two inputs to a NAND gate and the output of the First NAND gate goes again to an another NAND gate’s inputs.

=> s1 = (X.Y)’
=> s2 = (s1.s1)’ = s1’
=> s2 = ((X.Y)’)’
=> X.Y

3. NAND Gate to OR Gate Conversion

Refer the following Diagram

Digital : Image – NAND to OR

NAND to OR Conversion

NAND to OR Conversion

According to diagram –

s1 = (X.X)’ = X’
s2 = (Y.Y)’ = Y’
s3= (s1.s2)’ = (X’.Y’)’
=> (X’)’ + (Y’)’
=> X+Y

4. NAND Gate to NOR Gate Convertion

Refer the following Diagram

Digital : Image – NAND to NOR

NAND to NOR conversion

NAND to NOR conversion

According to diagram –

s1 = (X.X)’ = X’
s2 = (Y.Y)’ = Y’
s3= (s1.s2)’ = (X’.Y’)’
=> (X’)’ + (Y’)’
=> X+Y
s4 = (s3.s3)’ = s3’
=> (X + Y)’

5. NAND to XOR Gate

Digital : Image – 5

6. NAND to XNOR Gate

Digital : Image – 6



Posted in Digital Design | Tagged: , , , , , , , , , , , | 8 Comments »

What is the effect of AC and DC current with an inductor?

Posted by Nityanand Dubey on March 5, 2009


Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

Same as last chapter, to understand the behavior of a inductor with the AC and DC currents, we will take the help of the electronic symbols used for inductor, AC current and DC current .

To understand the effect of a inductor with the DC current, Lets See the following Image .

Image Inductor with DC

Inductor with DC

Inductor with DC

Now according to the diagram –

DC Waves are straight waves So they can easily pass through the tunnel built in the inductor

Now Lets see the next diagram, which describes the behavior of AC Current with the inductors

Image Inductor with AC

Inductor with AC

Inductor with AC

Now by looking into the image , It is clear that AC current tries to go though the Inductor but due to its specific structure, is scrambles with the inductor and could not pass through

So we can say that an inductor resists the AC current

Summary : The Inductor Blocks the AC Current but allows the DC current to pass though it

Mathematical Proof : By Puneet Arora

Resistance offered by an Inductor to a signal flowing through it:

R = 2πfl

where f = frequecy of the signal
l = value of the inductor

For a DC signal,

DC signal does not vary its value as an AC signal does.
Therefore, frequency of a DC signal,

f = 0HZ

This makes Inductor resistance R = 2πfl ~ zero

This makes it clear that an inductor offers no resistance to a DC signal.

FOR AN AC signal

AC signal is a time varying signal and attains positive and negative values periodically or non periodically. So it has a finite value of frequncy say f

Therefore resistance offered by an inductor to an AC signal

R = 2πfl = A finite value depending upon frequcncy of the AC signal.

Higher the frequecy of the AC signal, higher is the resistance offered.
So an inductor blocks high frequecy AC signals.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , , | Leave a Comment »

What is the effect of AC and DC current with a capacitor?

Posted by Nityanand Dubey on March 3, 2009

Please Note that the mentioned description is not the actual operation of the device. It is just a way to remember the concept .

To understand the behavior of a capacitor with the AC and DC current, we will Take the help of the Capacitor Symbol and the symbol of AC and DC currents.

Lets See the following Image .

Image Layman’s : 1

Ac on cap

Ac on cap

Now according to the diagram –

AC Waves can pass through the Capacitor because of its Specific Shape

Now Lets see the next diagram, which describes the behavior of DC Current with the capacitor

Image Layman’s : 2

DC on cap

DC on cap

Now According to the image, It is clear that DC current tries to go though the capacitor but is just crashes down by the Capacitor’s huge wall

So we can say that a capacitor breaks the DC Current

Summary : The Capacitor Blocks the DC Current but allows the AC current to pass though it

Mathematical Proof : By Puneet Arora

RESISTANCE OFFERED BY A CAPACITOR TO A SIGNAL FLOWING THROUGH IT:

R = 1/2πfc
where f = frequency of the signal
c = value of the capacitor

FOR A DC SIGNAL

DC signal does not vary its value as an AC signal does.
Therefore, frequency of a DC signal,

f = 0HZ

This makes Capacitor resistance R = 1/2πfc ~ infinite

This makes it clear that a capacitor blocks a DC signal.

FOR AN AC signal

AC signal is a time varying signal and attain positive and negative values periodically or non periodically. So it has a finite value of frequncy say f

Therefore resistance offered by a capacitor to an AC signal

R = 1/2πfc = A finite value depending upon frequcncy of the AC signal.

For higher frequency signal, resistance offered is very small.

If you have any idea similar to this, Please feel free to share it. It will be duly acknowledged in this site.

Posted in Layman's Electronincs | Tagged: , , , | 2 Comments »

What is the difference between a function and a task?

Posted by Nityanand Dubey on February 19, 2009

There are many differences in a function and a task in the verilog

1. Behavior :

Function : function call happens in real time OR no simulation delay can be inserted during the function call
Task : Tasks can be inserted with a delay

2. No of outputs :

Function : A function can have at least one input arg to be passed, and also it can have only one output to drive
Task : Task can have any no of inputs and outputs.

3. Nesting :

Function : A function can call a function inside it but not a task
Task : Task can call either a function or a task inside it.

4. Synthesis :

Function : A function can be synthesized
Task : Tasks are not synthesizable

5. Limitations :

Function : A function does not allow any delay, timing, event inside it
Task : Tasks can have delays, events inside it

6. Usage :

Function : A can be used for RTL as well as behavioral coding ( mostly for combinational logic)
Task : Tasks can be used for behavioral modeling only.

Posted in VERILOG | Tagged: , , , | Leave a Comment »

Vital Table Symbols for VHDL designs

Posted by Nityanand Dubey on December 9, 2008

During working with some vital designs, initially I felt many difficulties to understand the symbols used in the Vital State Table.

This vital table is refered from IEEE – VITAL ASIC modeling Specification –

Type VitalTableSymbolType is {

‘/’ — 0->1

‘’ — 1->0

‘P’ Union of ‘/’ and ‘^’ ( any edge to 1)

‘N’ Union of ‘’ and ‘v’ ( any edge to 0)

‘r’ — 0->X

‘f’ — 1->X

‘p’ Union of ‘/’ and ‘r’ ( any edge from 0)

‘n’ Union of ‘’ and ‘f’ ( any edge from 1)

‘R’ Union of ‘^’ and ‘p’ ( any possible rising edge)

‘F’ Union of ‘v’ and ‘n’ ( any possible falling edge)

‘^’ X->1

‘v’ — X->0

‘E’ Union of ‘v’ and ‘^’ ( any edge from X)

‘A’ Union of ‘r’ and ‘^’ ( rising edge to or from X)

‘D’ Union of ‘f’ and ‘v’ ( falling edge to or from X)

‘*’ Union of ‘R’ and ‘F’ ( any edge)

‘X’ — Unknown Level

‘0’ Low Level

‘1’ High Level

‘-’ Don’t Care

‘B’ 0 or 1

‘Z’ High Impedance

‘S’ Steady Value

};

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How can we take help from Front-End Simulators like ncverilog, modelsim, vcs etc.

Posted by Nityanand Dubey on October 10, 2008

Each EDA Tool assigns a warning or a error as it finds anything abnormal in the written code and due to severity of the warning/Error, it decides to proceed further or not.

Many times, the tool given messages are not comprehensive and user needs to know some more details about the reason of failures.


Here are some tool help techniques to find the help about the respective Error/warning/messages


  1. Simulator : NC-Verilog

NC-Verilog is a simulator provided by Cadence design system. It is a part of IUS package offered by the cadence. There is a utility (executable) present in this package in terms of providing quick details of messages. This utility is called “nchelp”


This executable path should be present in your executable path list. It can be checked with the “which” command


> which nchelp

/path/to/your/installation/area/bin/nchelp


If the utility is not in the path list, Either you can add it or also you can use the executable with the complete path (from installation area)

Usage :

> nchelp [options] tool error


Example :

Here is an example of error message –

ncelab: *W,SBNGL2 (./dut.v,1366|11): The sum of both limits in $setuphold or $recrem is less than the tolerance value: the negative limit will be set to zero.


Now If user wants to see the description of the error –


Ø nchelp ncelab SBNGL2

Here – ncelab is the utility for elaboration used by nc-verilog simulator

SBNGL2 – the Error Code


Output from this command –


nchelp: 08.10-s005: (c) Copyright 1995-2008 Cadence Design Systems, Inc.


ncelab/SBNGL2 =

The magnitude of the negative limit value minus the positive limit value in a $setuphold or $recrem timing check must be less than or equal to the tolerance value given by -ntc_tolerance option (by default, the tolerance value is 0).

The limits will be adjusted: by default, the negative limit will bet set to 0. However, if -ntc_neglim is specified, the negative limit will be adjusted to match the positive limit; if the -ntc_poslim is specified, the positive limit will be adjusted to match the negative value.


  1. Simulator : ModelSim

In ModelSim Simulator, It assigns an message number with all the messages. To get the details of the specific warning/error, User needs to use the associated number.

To provide help for debugging, ModelSim provides a Utility called “verror”


First User needs to be sure that the executable path is present in the global path list. This can be checked as

Ø which verror

This should show a valid path of executable “verror”

Now, User needs to write the Error number with this command


Syntax :

verror < message id>


Example

> veeror 3035


Output :

vsim Message # 3035:

This warning occurs when the level of an instantiation reaches a certain depth. It indicates that the instantiation might be recursive. A further attempt is made to complete the instantiation. If the maximum depth is reached then an elaboration error is generated.

Posted in ASIC Design Flow | Tagged: , , , , | Leave a Comment »

What is the difference between a Latch and a Flip-Flop

Posted by Nityanand Dubey on August 21, 2008

 

The Latches and Flop-flop, both are considered as a sequential element of Digital Design. It means the output of both blocks; depend on the input as well as the previous output.

Here are some difference between the latches and Flip-flops(FF)

1. Functionality : The Latches are level sensitive blocks, it means the output may change any time during the active phase of clock ( As input changes) In other hand the Flip-flops as edge sensitive and output changes only with the clock edge. In between it does not changes (even though input toggles)

2.  Area : The latches take less area than Flip-flops, Since the Flip-flops made of latches. The D Flip flop made of two latches in master-slave configuration.

3.  Speed: The latches are more faster than then the Flop flops, Since less number of gates used in the latches,

4. . Clock : Latches may of may not have clocks. But A Flip-flop must be having a clock.

Posted in Digital Design | Tagged: , , , , | 1 Comment »