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Posts Tagged ‘Modelsim’

How to pass parameters/generic values from the simulator’s command line

Posted by Nityanand Dubey on February 13, 2012


** Note: We have used common term parameters applicable for verilog designs. In VHDL the ‘Generics’ are used for the same.

We use different parameters/generics in the verilog/vhdl designs. Parameters give us huge re-usability of the codes. It means we can use same module/code various times in a big design and each time it’s behavior can be different.

For Example: If I have a parameterized module of a memory instance, where we can configure the length/width of the array by passing the number of words and number of bits through parameters, then we can use same code in various places of a design wherever the memory is needed and the configuration of the instance can be controlled by parameters.

Now, since we have only one module/code which is being used by all the other similar memory instances but different configuration

In the module/code, we provide some default values to the parameter. We need to overwrite the default parameters with the relevant values, If we want to use the module with various configurations,.

Here are the option used by different commonly used industry simulators (VCS, NC-Verilog and ModelSim)

ModelSim: The Parameters value can be passed with ‘vsim’ command in the ModelSim simulator

Assuming we want to supply a parameter value globally to all the modules

-g<param_name>=<param_value>

Example:  All the parameters present in the models named as “simulation_mode” should be active

-g_simulation_mode=yes

Here: “yes” is the value of simulation_mode  to make it as active.

 VCS –

For VCS, Let’s consider another example, say, I want memory ‘A’ with width of 16 bit and Memory ‘B’ width as 64

-pvalue+top/mem_A/No_of_bits=16  -pvalue+top/mem_B/No_of_bits=64

NC-Verilog: To perform same thing the ncverilog uses “defparam” syntax, let’s follow same example as we did in case of VCS –

If you are using 3 step NC-verilog command then following syntax will be used with “ncelab” command line.

Ncelab  […. Other options] -defparam  top.mem_A.No_of_bits=16  -defparam  top.mem_B.No_of_bits=64 

If you are using single step NC-Verilog command then the syntax will look like –

ncverilog [… other options …] +defparam+ top.mem_A.No_of_bits=16

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How can we take help from Front-End Simulators like ncverilog, modelsim, vcs etc.

Posted by Nityanand Dubey on October 10, 2008

Each EDA Tool assigns a warning or a error as it finds anything abnormal in the written code and due to severity of the warning/Error, it decides to proceed further or not.

Many times, the tool given messages are not comprehensive and user needs to know some more details about the reason of failures.


Here are some tool help techniques to find the help about the respective Error/warning/messages


  1. Simulator : NC-Verilog

NC-Verilog is a simulator provided by Cadence design system. It is a part of IUS package offered by the cadence. There is a utility (executable) present in this package in terms of providing quick details of messages. This utility is called “nchelp”


This executable path should be present in your executable path list. It can be checked with the “which” command


> which nchelp

/path/to/your/installation/area/bin/nchelp


If the utility is not in the path list, Either you can add it or also you can use the executable with the complete path (from installation area)

Usage :

> nchelp [options] tool error


Example :

Here is an example of error message –

ncelab: *W,SBNGL2 (./dut.v,1366|11): The sum of both limits in $setuphold or $recrem is less than the tolerance value: the negative limit will be set to zero.


Now If user wants to see the description of the error –


Ø nchelp ncelab SBNGL2

Here – ncelab is the utility for elaboration used by nc-verilog simulator

SBNGL2 – the Error Code


Output from this command –


nchelp: 08.10-s005: (c) Copyright 1995-2008 Cadence Design Systems, Inc.


ncelab/SBNGL2 =

The magnitude of the negative limit value minus the positive limit value in a $setuphold or $recrem timing check must be less than or equal to the tolerance value given by -ntc_tolerance option (by default, the tolerance value is 0).

The limits will be adjusted: by default, the negative limit will bet set to 0. However, if -ntc_neglim is specified, the negative limit will be adjusted to match the positive limit; if the -ntc_poslim is specified, the positive limit will be adjusted to match the negative value.


  1. Simulator : ModelSim

In ModelSim Simulator, It assigns an message number with all the messages. To get the details of the specific warning/error, User needs to use the associated number.

To provide help for debugging, ModelSim provides a Utility called “verror”


First User needs to be sure that the executable path is present in the global path list. This can be checked as

Ø which verror

This should show a valid path of executable “verror”

Now, User needs to write the Error number with this command


Syntax :

verror < message id>


Example

> veeror 3035


Output :

vsim Message # 3035:

This warning occurs when the level of an instantiation reaches a certain depth. It indicates that the instantiation might be recursive. A further attempt is made to complete the instantiation. If the maximum depth is reached then an elaboration error is generated.

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