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Posts Tagged ‘timescale’

What is Timescale in verilog codes

Posted by Nityanand Dubey on March 18, 2009

The ‘timescale is one of the compiler directive to specify the unit for the delays used in the design with their precision.

The timescale line is very important in the verilog simulation, because there are no any default delays specified by the verilog.

Syntax :

`timescale <time unit>/<time precision>

Here :

time unit : This is the time to be used as one unit for all the delays used in the design.

time precision : This represents the minimum delay which needs to be considered during simulation or it decides that how many decimal point would be used with the time unit.

Range of Timescale :

The range for time unit can be from seconds to femto-seconds, which includes all the time units including s (second), ms(mili-second), us(micro-second), ns(nano-second), ps(pico-second) and fs(femto-second).

Example :

`timescale 1ns/1ps

Here :

1ps = 0.001 ns

#1; // = 1ns delay

#1.003; // = will be considered as a valid delay

#1.0009; // = will be taken as 1 ns only since it is out of the precision value.

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Posted in VERILOG | Tagged: , , , | 3 Comments »