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Posts Tagged ‘verilog code for DFF’

Design synthesis and relevant verilog code for DFF

Posted by Nityanand Dubey on March 31, 2009

For RTL Coding, one should know that what code will infer which hardware in the design and vise versa.

The Design engineer should be aware of relevant code and the output logic so he can be able to minimize the design and the no of gates using.

In this post we will see deferent DFF and their verilog codes

DFF ( D- Flip-Flop)

reg q;

always @ (posedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the posegde of the clock and it will remain untouched till next posedge of the clock since the q is defined as reg.

D-Flip Flop

D-Flip Flop

DFF ( D- Flip-Flop) with Asynchronous reset.

reg q;

always @ (posedge clk or posedge reset)
if (reset)
q <= 1’b0;
else
q <= d;

According to above code, the reset is positive edge triggered and asynchronous so it is kept in the sensitivity list of always block with the posedge.

Inside the always block, there are a conditional statement to check whether the reset is true (1), otherwise it behaves as normal DFF

DFF - Async Reset

DFF - Async Reset

DFF ( D- Flip-Flop) with synchronous reset

reg q;

always @ (posedge clk)
if (reset)
q <= 1’b0;
else
q <= d;

Synchronous reset means the flop will be reset only with the posedge of clock, hence the sensitivity list does not have the reset signal; However it check the reset for true whenever the posedg of clock comes.

DFF - Sync Reset

DFF - Sync Reset

DFF ( D- Flip-Flop) with gated clock.

reg q;
wire gtd_clk = enable && clk;

always @ (posedge gtd_clk)
q <= d;

Many times it becomes required to apply clock to the design only when the enable is active. This is done by the gated clock. The clock and enable both are the inputs to a and gate and the output of the gate goes to the clock input of the flop.

DFF - Gated Clock

DFF - Gated Clock

Data Enabled DFF

reg q;

always @ (posedge clk)
if (enable)
q <= d;

Data Enabled flops has a mux at the data input, which is controlled by the enable signal. Now even the posedge of clock comes to the flop, flop will not change the value until enable is not active.

DFF - Data Enable

DFF - Data Enable

Negative Edge triggered DFF

reg q;

always @ (negedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the negedge of the clock and it will remain untouched till next negedge of the clock since the q is defined as reg.

DFF -Negative Edge

DFF -Negative Edge



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