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Posts Tagged ‘VHDL’

How to pass parameters/generic values from the simulator’s command line

Posted by Nityanand Dubey on February 13, 2012


** Note: We have used common term parameters applicable for verilog designs. In VHDL the ‘Generics’ are used for the same.

We use different parameters/generics in the verilog/vhdl designs. Parameters give us huge re-usability of the codes. It means we can use same module/code various times in a big design and each time it’s behavior can be different.

For Example: If I have a parameterized module of a memory instance, where we can configure the length/width of the array by passing the number of words and number of bits through parameters, then we can use same code in various places of a design wherever the memory is needed and the configuration of the instance can be controlled by parameters.

Now, since we have only one module/code which is being used by all the other similar memory instances but different configuration

In the module/code, we provide some default values to the parameter. We need to overwrite the default parameters with the relevant values, If we want to use the module with various configurations,.

Here are the option used by different commonly used industry simulators (VCS, NC-Verilog and ModelSim)

ModelSim: The Parameters value can be passed with ‘vsim’ command in the ModelSim simulator

Assuming we want to supply a parameter value globally to all the modules

-g<param_name>=<param_value>

Example:  All the parameters present in the models named as “simulation_mode” should be active

-g_simulation_mode=yes

Here: “yes” is the value of simulation_mode  to make it as active.

 VCS –

For VCS, Let’s consider another example, say, I want memory ‘A’ with width of 16 bit and Memory ‘B’ width as 64

-pvalue+top/mem_A/No_of_bits=16  -pvalue+top/mem_B/No_of_bits=64

NC-Verilog: To perform same thing the ncverilog uses “defparam” syntax, let’s follow same example as we did in case of VCS –

If you are using 3 step NC-verilog command then following syntax will be used with “ncelab” command line.

Ncelab  […. Other options] -defparam  top.mem_A.No_of_bits=16  -defparam  top.mem_B.No_of_bits=64 

If you are using single step NC-Verilog command then the syntax will look like –

ncverilog [… other options …] +defparam+ top.mem_A.No_of_bits=16

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Vital Table Symbols for VHDL designs

Posted by Nityanand Dubey on December 9, 2008

During working with some vital designs, initially I felt many difficulties to understand the symbols used in the Vital State Table.

This vital table is refered from IEEE – VITAL ASIC modeling Specification –

Type VitalTableSymbolType is {

‘/’ — 0->1

‘’ — 1->0

‘P’ Union of ‘/’ and ‘^’ ( any edge to 1)

‘N’ Union of ‘’ and ‘v’ ( any edge to 0)

‘r’ — 0->X

‘f’ — 1->X

‘p’ Union of ‘/’ and ‘r’ ( any edge from 0)

‘n’ Union of ‘’ and ‘f’ ( any edge from 1)

‘R’ Union of ‘^’ and ‘p’ ( any possible rising edge)

‘F’ Union of ‘v’ and ‘n’ ( any possible falling edge)

‘^’ X->1

‘v’ — X->0

‘E’ Union of ‘v’ and ‘^’ ( any edge from X)

‘A’ Union of ‘r’ and ‘^’ ( rising edge to or from X)

‘D’ Union of ‘f’ and ‘v’ ( falling edge to or from X)

‘*’ Union of ‘R’ and ‘F’ ( any edge)

‘X’ — Unknown Level

‘0’ Low Level

‘1’ High Level

‘-’ Don’t Care

‘B’ 0 or 1

‘Z’ High Impedance

‘S’ Steady Value

};

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What is the difference between signals and variables

Posted by Nityanand Dubey on July 7, 2008

There are three major difference between a signal and a variable in the VHDL

 Coverage wise –

Signals has coverage to whole architecture, it can be access from any place in a Architecture of entity

A variable is local to a procedure defined in the architecture

Behavior wise

Signal assignments executes concurrently, It means, if we have 5 signals assignment, then it depends on the simulator to decide which signal to be assigned first

In case of variable, it takes the value immediately OR in other language, it executes sequentially

Synthesis Wise –

If we have 2 variable and two signals used in a process, the variables infer just a wire during synthesis, but the signals infer a Flop.

 Also you can say that – the number of flops inferred by a process is roughly equal to the number of signals used in it (in Left had side)

 

 

 

 

 

Posted in VHDL | Tagged: , , , , , | 1 Comment »